Isolation structures are well known in the art as a means of electrically insulating active semiconductor devices which have been fabricated on the same substrate. In order to reduce device-to-device spacing, trench isolation structures have been proposed.
For example, U.S. Pat. No. 5,592,792 to Corboy et al discloses a method of fabricating a trench isolation structure. However, the resulting structure has a faceted upper surface which impedes further planar processing, planarization being important to the efficiency of producing miniaturized semiconductor structures. Moreover, the Corboy et al isolation device does not provide an effective means of complete isolation.
Certain inventors have addressed the problem of forming a planar isolation structure on a substrate containing multiple devices. For instance, U.S. Pat. No. 4,680,614, U.S. Pat. No. 4,528,047, U.S. Pat. No. 4,689,656 and U.S. Pat. No. 4,526,631, among others, addresses various aspects of producing isolation trenches having a planar upper surface. However, these patents teach complex fabrication methods which require cumbersome and expensive multi-step processing and result in multi-layered filling of the isolation trenches.
Consequently, a need exists for an isolation structure which can be formed simply, efficiently, and inexpensively and which effectively isolates the active devices between which the structure is fabricated.